Adds data server (WIP)data_improvements

1 files changed, 26 insertions, 92 deletions

diff --git a/arch/v1/arch.c b/arch/v1/arch.c
index 39cfe15..152a97d 100644
--- a/arch/v1/arch.c
+++ b/arch/v1/arch.c
@@ -42,14 +42,13 @@ void arch_core_save(FILE *f, const struct Core *core) {
 
     fwrite(core->iexe, sizeof(uint64_t), INST_COUNT, f);
     fwrite(core->iwrt, sizeof(uint64_t), INST_COUNT, f);
-    fwrite(&core->emb0, sizeof(uint64_t), 1, f);
-    fwrite(&core->emb1, sizeof(uint64_t), 1, f);
-    fwrite(&core->eliv, sizeof(uint64_t), 1, f);
-    fwrite(&core->edea, sizeof(uint64_t), 1, f);
     fwrite(&core->wmb0, sizeof(uint64_t), 1, f);
     fwrite(&core->wmb1, sizeof(uint64_t), 1, f);
     fwrite(&core->wdea, sizeof(uint64_t), 1, f);
-    fwrite(core->aeva, sizeof(uint64_t), MVEC_SIZE, f);
+
+#if defined(DATA_PUSH_PATH)
+    //fwrite(core->weva, sizeof(uint64_t), MVEC_SIZE, f);
+#endif
 }
 #endif
 
@@ -60,14 +59,13 @@ void arch_core_load(FILE *f, struct Core *core) {
 
     fread(core->iexe, sizeof(uint64_t), INST_COUNT, f);
     fread(core->iwrt, sizeof(uint64_t), INST_COUNT, f);
-    fread(&core->emb0, sizeof(uint64_t), 1, f);
-    fread(&core->emb1, sizeof(uint64_t), 1, f);
-    fread(&core->eliv, sizeof(uint64_t), 1, f);
-    fread(&core->edea, sizeof(uint64_t), 1, f);
     fread(&core->wmb0, sizeof(uint64_t), 1, f);
     fread(&core->wmb1, sizeof(uint64_t), 1, f);
     fread(&core->wdea, sizeof(uint64_t), 1, f);
-    fread(core->aeva, sizeof(uint64_t), MVEC_SIZE, f);
+
+#if defined(DATA_PUSH_PATH)
+    //fread(core->weva, sizeof(uint64_t), MVEC_SIZE, f);
+#endif
 }
 #endif
 
@@ -123,9 +121,6 @@ void _free_memory_block(struct Core *core, uint64_t addr, uint64_t size) {
 
     for (uint64_t i = 0; i < size; ++i) {
         mvec_free(core, addr + i);
-
-        // Record deallocation event
-        ++core->aeva[addr];
     }
 }
 
@@ -388,9 +383,6 @@ void _alloc(struct Core *core, uint64_t pix, bool fwrd) {
     // Free (non-allocated) byte found, enlarge child block 1 byte
     mvec_alloc(core, proc->sp);
 
-    // Record allocation event
-    ++core->aeva[proc->sp];
-
     if (!proc->mb1s || !fwrd) {
         proc->mb1a = proc->sp;
     }
@@ -687,19 +679,9 @@ void arch_proc_step(struct Core *core, uint64_t pix) {
     struct Proc *proc = proc_fetch(core, pix);
     uint8_t inst = _get_inst(core, proc->ip);
 
-    // Store execute event
+    // Store specific instruction execution event in database
     ++core->iexe[inst];
 
-    if (mvec_is_in_mb0_of_proc(core, proc->ip, pix)) {
-        ++core->emb0;
-    } else if (mvec_is_in_mb1_of_proc(core, proc->ip, pix)) {
-        ++core->emb1;
-    } else if (mvec_is_alloc(core, proc->ip)) {
-        ++core->eliv;
-    } else {
-        ++core->edea;
-    }
-
     // Execute instruction
     switch (inst) {
     case jmpb:
@@ -835,25 +817,16 @@ const char *arch_mnemonic(uint8_t inst) {
 // Data aggregation functions
 // ----------------------------------------------------------------------------
 #if defined(DATA_PUSH_PATH)
+#if defined(COMMAND_NEW)
 void arch_push_data_header() {
     assert(g_sim_data);
 
-    g_info("Creating 'trend' table in SQLite database");
+    g_info("Creating 'arch_general' table in SQLite database");
     salis_exec_sql(
         0, NULL, NULL,
-        "create table trend ("
+        "create table arch_general ("
 #define FOR_CORE(i) \
         "cycl_" #i " int not null, " \
-        "mall_" #i " int not null, " \
-        "pnum_" #i " int not null, " \
-        "pfst_" #i " int not null, " \
-        "plst_" #i " int not null, " \
-        "amb0_" #i " real not null, " \
-        "amb1_" #i " real not null, " \
-        "emb0_" #i " int not null, " \
-        "emb1_" #i " int not null, " \
-        "eliv_" #i " int not null, " \
-        "edea_" #i " int not null, " \
         "wmb0_" #i " int not null, " \
         "wmb1_" #i " int not null, " \
         "wdea_" #i " int not null, "
@@ -887,7 +860,7 @@ void arch_push_data_header() {
     }
 
     // Memory events
-    char *eprefs[] = { "aev" };
+    char *eprefs[] = { /* "wev" */ };
     int eprefs_cnt = sizeof(eprefs) / sizeof(eprefs[0]);
 
     for (int i = 0; i < CORES; ++i) {
@@ -908,30 +881,17 @@ void arch_push_data_header() {
         }
     }
 }
+#endif
 
 void arch_push_data_line() {
     assert(g_sim_data);
 
-    // Instruction population
+    // Measure instruction population
     uint64_t ipop[CORES][INST_COUNT] = { 0 };
 
-    // Average memory block sizes
-    double amb0[CORES] = { 0 };
-    double amb1[CORES] = { 0 };
-
     for (int i = 0; i < CORES; ++i) {
         struct Core *core = &g_cores[i];
 
-        for (uint64_t j = core->pfst; j <= core->plst; ++j) {
-            const struct Proc *proc = proc_get(core, j);
-
-            amb0[i] += (double)proc->mb0s;
-            amb1[i] += (double)proc->mb1s;
-        }
-
-        amb0[i] /= core->pnum;
-        amb1[i] /= core->pnum;
-
         for (uint64_t j = 0; j < MVEC_SIZE; ++j) {
             ++ipop[i][_get_inst(core, j)];
         }
@@ -947,22 +907,12 @@ void arch_push_data_line() {
 #endif
     }
 
-    g_info("Pushing row to 'trend' table in SQLite database");
+    g_info("Pushing row to 'arch_general' table in SQLite database");
     salis_exec_sql(
         0, NULL, NULL,
-        "insert into trend ("
+        "insert into arch_general ("
 #define FOR_CORE(i) \
         "cycl_" #i ", " \
-        "mall_" #i ", " \
-        "pnum_" #i ", " \
-        "pfst_" #i ", " \
-        "plst_" #i ", " \
-        "amb0_" #i ", " \
-        "amb1_" #i ", " \
-        "emb0_" #i ", " \
-        "emb1_" #i ", " \
-        "eliv_" #i ", " \
-        "edea_" #i ", " \
         "wmb0_" #i ", " \
         "wmb1_" #i ", " \
         "wdea_" #i ", "
@@ -970,23 +920,13 @@ void arch_push_data_line() {
 #undef FOR_CORE
         "step"
         ") values ("
-#define FOR_CORE(i) "%ld, %ld, %ld, %ld, %ld, %f, %f, %ld, %ld, %ld, %ld, %ld, %ld, %ld, "
+#define FOR_CORE(i) "%ld,  %ld, %ld, %ld, "
         FOR_CORES
 #undef FOR_CORE
         "%ld"
         ");",
 #define FOR_CORE(i) \
         g_cores[i].cycl, \
-        g_cores[i].mall, \
-        g_cores[i].pnum, \
-        g_cores[i].pfst, \
-        g_cores[i].plst, \
-        amb0[i], \
-        amb1[i], \
-        g_cores[i].emb0, \
-        g_cores[i].emb1, \
-        g_cores[i].eliv, \
-        g_cores[i].edea, \
         g_cores[i].wmb0, \
         g_cores[i].wmb1, \
         g_cores[i].wdea,
@@ -1000,7 +940,7 @@ void arch_push_data_line() {
 
     for (int i = 0; i < CORES; ++i) {
         for (int j = 0; j < iprefs_cnt; ++j) {
-            uint64_t *ia;
+            uint64_t *ia = NULL;
 
             if (!strcmp("pop", iprefs[j])) {
                 ia = ipop[i];
@@ -1043,17 +983,17 @@ void arch_push_data_line() {
         }
     }
 
-    char *eprefs[] = { "aev" };
+    // TODO: insert write memory events
+    char *eprefs[] = { /* "wev" */ };
     int eprefs_cnt = sizeof(eprefs) / sizeof(eprefs[0]);
 
-    // TODO: insert memory events
     for (int i = 0; i < CORES; ++i) {
         for (int j = 0; j < eprefs_cnt; ++j) {
-            uint64_t *in;
+            uint64_t *in = NULL;
 
-            if (!strcmp("aev", eprefs[j])) {
-                in = g_cores[i].aeva;
-            }
+            //if (!strcmp("wev", eprefs[j])) {
+            //    in = g_cores[i].weva;
+            //}
 
             // Compress event data
             size_t size = sizeof(uint64_t) * MVEC_SIZE;
@@ -1104,23 +1044,17 @@ void arch_push_data_line() {
         }
     }
 
-    // Reset data aggregation fields
+    // Reset arch-specific data aggregation fields
     for (int i = 0; i < CORES; ++i) {
         struct Core *core = &g_cores[i];
 
         memset(core->iexe, 0, sizeof(uint64_t) * INST_COUNT);
         memset(core->iwrt, 0, sizeof(uint64_t) * INST_COUNT);
 
-        core->emb0 = 0;
-        core->emb1 = 0;
-        core->eliv = 0;
-        core->edea = 0;
         core->wmb0 = 0;
         core->wmb1 = 0;
         core->wdea = 0;
 
-        memset(core->aeva, 0, sizeof(uint64_t) * MVEC_SIZE);
-        //memset(core->eeva, 0, sizeof(uint64_t) * MVEC_SIZE);
         //memset(core->weva, 0, sizeof(uint64_t) * MVEC_SIZE);
     }
 }